1. Field of the Invention
The present invention relates to a trench gate MOS semiconductor device that is used in, for example, a power conversion apparatus and a method for manufacturing the same, and more particularly, to an insulated gate bipolar transistor with a trench gate structure.
2. Background of the Related Art
A technique for reducing the power consumption of a power conversion apparatus has been developed. Particularly, there are great expectations for a technique for reducing the power consumption of a power device which plays a central role. Among the power devices, an insulated gate bipolar transistor (hereinafter, referred to as an IGBT) which can achieve a low on-voltage using a conductivity modulation effect and easily control the gate for voltage driving has been generally used.
A planar gate structure and a trench gate structure have been known as the gate structure of the IGBT. In the planar gate structure, for example, a planar conductive polysilicon electrode (hereinafter, simply referred to as a polysilicon electrode in some cases) which is formed over the surface of a wafer, with a gate oxide film interposed therebetween, is used as a gate electrode. In the trench gate structure, for example, a polysilicon electrode which is provided in a trench that is vertically formed in the depth direction from the surface of the wafer, with a gate oxide film interposed therebetween, is used as a gate electrode.
An IGBT with the trench gate structure (hereinafter, referred to as a trench gate IGBT) has a structure in which a channel that is a current path is formed in a p-type base region provided along the side wall surface of the trench when the IGBT is turned on. Therefore, in the trench gate IGBT, it is possible to increase channel density using, for example, a relatively simple method of reducing the gap between the trenches. The increase in channel density makes it possible to further reduce the on-voltage. Therefore, in recent years, the use of the IGBT with the trench gate structure has increased.
Various improvement methods have been proposed in order to further reduce the on-voltage of the trench gate IGBT. For example, JP 5-243561 A (Patent Document 1, see FIG. 101) discloses an injection enhanced gate bipolar transistor (IEGT). The IEGT has limitation characteristics close to the on-voltage of the diode.
The structure of the IEGT device is characterized in that the surface of an n+ emitter region and the surface of a portion of a p-type base region are covered with an insulating film and there is a region (hereinafter, referred to as a p-type floating region) with which an emitter electrode does not come into electrical contact. When the IEGT is turned on, holes which are injected from the collector are less likely to be discharged to the emitter electrode and are likely to be stored below (on the drift layer side) the p-type floating region that is electrically insulated from the emitter electrode. As a result, the carrier concentration distribution of an n-type drift layer of the IEGT is close to the carrier concentration distribution of a diode and the on-voltage can be lower than that of a general trench gate IGBT.
On the other hand, the power device requires high-speed switching characteristics in addition to the low on-voltage and it is also important to improve the switching characteristics. However, in the trench gate IGBT and the IEGT, as the density of the trench structure increases in order to reduce the on-voltage, the gate capacitance increases and the switching characteristics deteriorate. That is, in the trench gate IGBT, it is necessary to charge and discharge the capacitance between the gate and the emitter and the capacitance between the gate and the collector when the trench gate IGBT is turned on and off, respectively. Therefore, when the gate capacitance increases, the charge and discharge time increases and the switching characteristics deteriorate. In addition, the deterioration of the switching characteristics means an increase in switching loss. The total loss of the power device is the sum of steady loss which is determined by the on-voltage and switching loss which occurs when the trench gate IGBT is turned on and off. Therefore, it is important to reduce the on-voltage and the switching loss, that is, the gate capacitance in order to reduce the total loss.
However, in the IEGT, the gate capacitance is substantially equal to the capacitance (mirror capacitance) between the gate and the collector, which causes an increase in turn-on loss. For the mirror capacitance, when the IGBT with the general trench gate structure is turned on and the gate voltage increases, first, the capacitance between the gate and the emitter is changed and then the capacitance (mirror capacitance) between the gate and the collector is changed. However, since the IEGT includes the p-type floating region, the gate capacitance is substantially equal to the capacitance (mirror capacitance) between the gate and the collector.
There are the following documents related to a reduction in the switching loss of the IGBT. FIG. 3 is a cross-sectional view illustrating a main portion of a cross-sectional structure taken along the line B1-B2 of FIG. 4. FIG. 4 is a plan view illustrating a main portion of a polysilicon gate electrode of a trench gate IGBT including a p-type floating region according to the related art. FIG. 3, for example, corresponding to FIG. 1 in JP 2001-308327 A (Patent Document 2), illustrates a main portion of the cross-sectional structure of an n-channel trench gate IGBT 100 including trenches which are arranged in a stripe-shaped plane pattern.
The IGBT 100 illustrated in FIG. 3 is characterized in that it has an IEGT structure. The IEGT structure includes an active region 112 that has a p-type base region 103 interposed between adjacent trenches 110 and an n+ emitter region 104 selectively formed in the p-type base region 103 and a p-type floating region 111 that does not have the n+ emitter region 104 formed in the p-type base region 103. The trench 110 has a depth that reaches an n− drift layer 102 from the surface of the n+ emitter region 104 through the p-type base region 103. A gate electrode 106 (hatched) which is a polysilicon electrode is provided in the trench 110, with a gate oxide film 105 interposed therebetween. An interlayer insulating film 107 covers the upper part of the gate electrode 106 to hold the insulation of the gate electrode 106 from an emitter electrode 108 which is provided on the interlayer insulating film 107. The n− drift layer 102 is formed on the front surface of a p+ substrate 101 by epitaxial growth and a collector electrode 109 is formed on the rear surface of the p+ substrate 101.
Therefore, when the IGBT is turned on, holes are less likely to be discharged to the emitter electrode 108 and are stored in the vicinity of the lower side of the p-type floating region 111. As a result, as described above, the carrier concentration distribution of the n− drift layer 102 is close to the carrier concentration distribution of the diode and the effect of reducing the on-voltage is obtained (for example, see Patent Document 2).
It has been reported that the turn-on characteristics need to be improved in M. Yamaguchi et al., “IEGT Design Criterion for Reducing EMI Noise”, in Proc. ISPSD′ 2004 pp. 115-118, 2004 (Non-patent Document 1, see the Abstract), which is common to the structure disclosed in Patent Document 2 and the structure disclosed in Patent Document 1.
U.S. Pat. No. 6,815,769 (Patent Document 3, see FIG. 1) discloses a structure which further improves the turn-on characteristics of the IGBTs (IEGTs) disclosed in Patent Document 1 and Patent Document 2. FIG. 5 is a cross-sectional view illustrating a main portion of the trench gate IGBT according to the related art. FIG. 5 corresponds to FIG. 1 in Patent Document 3. That is, one polysilicon electrode is not provided in the trench 215 illustrated in FIG. 5, but the polysilicon electrode is divided into two polysilicon electrodes 222a and 222b in a central portion of the trench 215 along the side wall of the trench 215. Of the divided polysilicon electrodes 222a and 222b, only the divided polysilicon electrode 222a which is close to the n+ emitter region 219 and the p-type base region 217 (close to the active region 210) is used as an effective gate electrode and the divided polysilicon electrode 222b which is close to the p-type floating region 220 is not connected to the gate electrode, but is connected to the emitter electrode 224.
Patent Document 3 also discloses a method for dividing the polysilicon electrode. That is, first, a polysilicon electrode is formed with a thickness that does not fill up the trench 215. With the polysilicon electrode remaining on the surface of the substrate, the polysilicon electrode in the bottom of the trench is etched, using the oxide film as a mask, to form the divided polysilicon electrodes 222a and 222b on both side walls. In addition, for example, a silicon oxide film 223 is filled between the divided polysilicon electrodes 222a and 222b in the trench 215 to insulate the divided polysilicon electrodes 222a and 222b on both side walls. Then, a lead portion from the polysilicon electrode on the surface of the substrate is formed. Reference numeral 212 indicates a collector electrode, reference numeral 213 indicates a collector layer, reference numeral 214 indicates a drift layer, reference numeral 216 indicates a gate oxide film, and reference numeral 225 indicates an interlayer insulating film.
In addition, a structure has been proposed in which a gate electrode provided in a trench has a cavity that is surrounded by a gate insulating film provided in the bottom of the trench, an interlayer insulating film provided at the top of the trench, and an electrode film provided on both side walls, in order to form a semiconductor device with a high-reliability trench gate structure, for example, see JP 2005-243932 A (Patent Document 4, FIG. 1 and paragraph 0012).
As disclosed in the above-mentioned Patent Document 3, in the method for forming the divided polysilicon electrodes 222a and 222b in the trench 215, the silicon oxide film 223 for insulation is filled between the divided polysilicon electrodes 222a and 222b. However, cyclic compression and tensile stress are applied to the silicon oxide film 223 and the divided polysilicon electrodes 222a and 222b by a thermal history during a manufacturing process, from the difference between the thermal expansion coefficients of the divided polysilicon electrodes 222a and 222b and the silicon oxide film 223 interposed therebetween. As a result, there is a concern that the gate characteristics will deteriorate or cracks will occur in the silicon oxide film 223, the divided polysilicon electrodes 222a and 222b, or the silicon substrate, resulting in an increase in leakage current. In addition, when the IGBT is turned on, the gate capacitance is increased by the silicon oxide film 223 (insulating film) interposed between the divided polysilicon electrodes 222a and 222b and the switching characteristics deteriorate.
The above-mentioned Patent Document 4 discloses a structure in which a cavity is provided between the divided gate electrodes to suppress the occurrence of stress due to the thermal history and to reduce the gate capacitance in the trench gate MOSFET, in order to solve the problem of the cracks due to stress or the deterioration of the characteristics. As disclosed in the above-mentioned Patent Document 4, in the structure in which the polysilicon electrode is simply divided into two electrodes, no problem occurs in the insulation between the divided polysilicon electrodes. However, in a structure in which one of the divided polysilicon electrodes is connected to the gate electrode and the other divided polysilicon electrodes is connected to the emitter electrode, the sufficient insulation between the two polysilicon electrode is not achieved only by the cavity.
The invention has been made in order to solve the above-mentioned problems. An object of the invention is to provide a trench gate MOS semiconductor device that can ensure insulation between divided polysilicon electrodes connected to different electrodes in a trench, reduce stress, and suppress an increase in gate capacitance due to an insulating film and a method for manufacturing the same.